Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material

ABSTRACT

A semiconductor device includes a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. The semiconductor device also includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of co-pending application Ser. No. 13/192,164, filed Jul. 27, 2011, which claimed priority from German patent application No. 10 2010 063 294.5, filed Dec. 16, 2010.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to metallization systems comprising sophisticated dielectric and conductive materials.

2. Description of the Related Art

In the field of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect structures electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect structures are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, usually a plurality of stacked wiring layers, also referred to as metallization layers, is provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. The vertical connections and the metal lines may also commonly be referred to as interconnect structures. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect structures are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.

Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm² in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the low-k dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper. Furthermore, the conductive barrier layers may also form highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current-induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds, with nitrogen and silicon and the like, are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.

Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or via openings which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and via openings is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and nonconductive barrier layers, the copper microstructure and the like, and their mutual interaction on the characteristics of the interconnect structure as a whole so as to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in metallization systems for various configurations so as to maintain device reliability for every new device generation or technology node.

Accordingly, a great deal of effort is being made in investigating the degradation of copper interconnects, especially in combination with low-k dielectric materials or ultra low-k (ULK) materials having a relative permittivity of 3.0 or even less, in order to find new materials and process strategies for forming copper-based lines and vias with a low overall permittivity and superior reliability.

One failure mechanism which is believed to significantly contribute to a premature device failure is the electromigration-induced material transport particularly along an interface formed between the copper and any barrier materials and a dielectric cap layer, which may be provided on the sidewalls and at the top of the core metal.

Consequently, the conductive barrier material may not only have to provide superior adhesion and copper diffusion blocking capabilities, but may also have to provide strong interfaces with the copper core metal in order to reduce the current-induced copper diffusion along the interface areas and also to substantially avoid material diffusion through any barrier layers. Upon further device scaling, in particular the characteristics of the conductive barrier materials may gain in importance since typically the thickness of the barrier materials may not scale in the same manner as the overall lateral dimensions of the interconnect structures have to be reduced. That is, in view of a reliable coverage of any inner surface areas of the interconnect structures, a certain minimum thickness may have to be preserved in order to reliably cover any critical sidewall areas, such as lower portions of via openings and the like. Consequently, the layer thickness may be significantly greater in less critical areas, thereby reducing the effective cross-sectional size of the resulting interconnect features. Hence, upon further scaling of the interconnect structure, the specific resistivity of these structures may increase due to a relative increase of the conductive barrier material with respect to the actual highly conductive core metal. For this reason, great efforts are being made in reducing the thickness of the conductive barrier layer systems while not unduly affecting the overall electromigration performance. It appears, however, that required electromigration behavior in combination with a desired low resistivity of the resulting interconnect structures may be difficult to achieve on the basis of well-established barrier layer systems comprising tantalum and tantalum nitride.

The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Basically, the present disclosure provides semiconductor devices and manufacturing techniques in which highly conductive fill metals, such as copper, copper alloys, silver and the like, may be reliably confined on the basis of a conductive barrier material which may provide superior electromigration behavior and reduced electrical resistivity compared to conventional tantalum-based barrier layer systems. To this end, a copper/silicon-containing material may be provided as an interface between dielectric material and the highly conductive core metal, thereby taking advantage of the superior material characteristics of a copper/silicon compound. Hereinafter, a silicon and copper-containing conductive material with a copper concentration of 5 atomic percent or more and a silicon content of 5 atomic percent or more may be referred to as copper silicide, irrespective of the actual stoichiometric composition of the silicon/copper compound. Furthermore, the silicon/copper compound may also include other atomic species, which in some illustrative embodiments may be present with a concentration of 5 atomic percent or less, wherein any such material composition may also be referred to as a copper silicide. It is well known that a copper silicide material may have superior electromigration performance, for instance compared to tantalum and tantalum nitride, thereby providing superior stability during a typical stress situation, as may occur during the operation of complex semiconductor devices. Hence, the current-induced or stress-induced copper diffusion may be efficiently blocked by the copper silicide material, even if provided with a reduced thickness compared to conventional conductive barrier material systems. Furthermore, the electrical conductivity is higher compared to the conventionally used tantalum/tantalum nitride barrier system, thereby enhancing electrical performance and in particular reducing the resistance between vias and metal lines, which may conventionally suffer from the moderately high resistivity of the tantalum/tantalum nitride barrier material. The silicon/copper compound may be formed on the basis of well-established process strategies, such as a silicidation on the basis of a silicon-containing process ambient, which may be provided in the form of plasma ambient and the like. In other illustrative embodiments disclosed herein, the silicon species may be provided by depositing a dedicated layer, which may be provided prior to or after depositing a copper-containing material layer in order to initiate a silicidation process. Consequently, the silicon/copper compound may be provided with high controllability, thereby contributing to enhanced reliability and superior electrical performance.

In one illustrative embodiment, a semiconductor device is disclosed that includes, among other things, a first metallization layer positioned above a substrate of the semiconductor device, the metallization layer including a dielectric material and a copper-containing metal region embedded in the dielectric material. Additionally, the exemplary semiconductor device includes a conductive barrier layer positioned along substantially an entirety of an interface between the copper-containing metal region and the dielectric material, the conductive barrier layer including a copper/silicon compound that is in direct contact with the dielectric material along substantially the entirety of the interface.

Another exemplary semiconductor device is disclosed that includes a layer of dielectric material positioned above a semiconductor substrate and an interconnect structure embedded in the layer of dielectric material. The embedded interconnect structure includes, among other things, a metal region and a copper silicide barrier layer positioned between the layer of dielectric material and the metal region, wherein the copper silicide barrier layer extends along substantially an entirety of an interface between the metal region and the layer of dielectric material, and the copper silicide barrier layer is in direct contact with the layer of dielectric material along substantially the entirety of the interface.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIG. 1 a schematically illustrates a cross-sectional view of a semiconductor device with a metallization system receiving a superior barrier material layer comprising a copper-silicon compound in combination with a highly conductive core metal, such as copper, according to illustrative embodiments;

FIGS. 1 b-1 c schematically illustrate a portion of the metallization system according to illustrative embodiments in which the silicon/copper compound material may be formed by depositing a copper material and exposing the material to a silicon-containing process ambient in order to initiate a silicidation reaction;

FIGS. 1 d-1 e schematically illustrate the semiconductor device according to further illustrative embodiments in which a silicon-containing material layer may be deposited, followed by a copper layer in order to initiate a silicidation process to form the copper/silicon-containing barrier layer;

FIG. 1 f schematically illustrates the semiconductor device according to still further illustrative embodiments in which a dedicated carrier material including a silicon species may be formed on a copper layer so as to initiate a silicon and copper interdiffusion in order to form the copper silicide barrier material; and

FIG. 1 g schematically illustrates the semiconductor device in a further advanced manufacturing stage in which a copper-based interconnect structure may be formed so as to include a copper silicide barrier material, according to still further illustrative embodiments.

While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

Generally, the present disclosure addresses the problem of reduced reliability and electrical performance of complex metallization systems caused by barrier material systems, such as tantalum, tantalum nitride barrier systems. To this end, in some illustrative embodiments disclosed herein, the usage of conventional tantalum-based barrier systems may be avoided by providing a conductive barrier material in the form of a copper/silicon compound, which may also be referred to as a copper silicide, which may per se provide superior electromigration performance compared to tantalum and tantalum nitride, while at the same time the electrical conductivity may be higher compared to conventional barrier systems. In this manner, for a given thickness and for given lateral dimensions of complex interconnect structures, a reduced overall resistance may be obtained, in particular at an interface between a via and a lower-lying metal line, while at the same time the copper silicide may provide superior electromigration characteristics, i.e., the current-induced metal diffusion along and through inner surface areas of the interconnect structure may be reduced compared to conventional barrier systems.

In some illustrative embodiments disclosed herein, the copper/silicon compound may be formed by providing a copper layer with a desired thickness, for instance on the basis of sputter deposition, electrochemical deposition and the like, which may subsequently be converted into a copper silicide by exposing the copper layer to a silicon-containing process ambient, for instance established on the basis of a plasma ambient including precursor gases, such as silane and any related gases, while in other cases a thermally activated gaseous ambient may be established, for instance on the basis of HMDS (hexamethyldisilazan), or derivatives thereof, which may represent well-established chemicals, for instance for treating sophisticated low-k dielectric materials in order to reduce etch-related damage in any such materials. In other illustrative embodiments, the silicon-containing process ambient may be established by forming a specific silicon-containing material layer on a copper layer and initiating a corresponding copper silicon interdiffusion in order to form the desired copper/silicon compound. For example, triazol or any derivatives thereof are well established chemicals for treating copper surfaces and may adhere to any exposed copper surface areas so as to form well-defined surface layers thereon. Moreover, these chemicals may also be prepared so as to include silicon or any other functional groups, which may thus adhere to the copper surface in a well-controllable manner. In a next step, the silicon species may be released, for instance by decomposing the carrier material, which may be accomplished by using elevated temperatures, radiation, such as UV radiation and the like. Consequently, in the subsequent silicon diffusion, a well-controlled amount of silicon species may be incorporated into the copper layer in order to form copper silicide in a highly controlled manner.

In still other illustrative embodiments, the copper/silicon compound may be formed by applying a silicon-containing material layer, such as a silicon layer, and thereafter a copper-containing layer may be formed on the silicon-containing layer in order to initiate a silicon/copper interdiffusion, thereby also forming the desired copper silicide barrier material. Thereafter, the actual fill or core metal, such as copper, may be deposited on the basis of any appropriate deposition techniques, such as electrochemical deposition techniques, wherein the copper silicide material may be used as a catalyst layer or seed layer. In other cases, if desired, a dedicated seed layer may be formed on the copper silicide material in order to further enhance the subsequent deposition of the actual fill metal.

FIG. 1 a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage in which a metallization system 150 may be formed above a device level 120 of the semiconductor device 100. The device level 120 may be understood as comprising at least one semiconductor layer, in and above which corresponding semiconductor-based circuit elements 121 are formed, such as transistors, capacitors and the like, as required according to specific circuit assembly of the device 100. Moreover, an appropriate substrate 101, such as a semiconductor substrate in the form of a silicon material and the like, may be provided according to the overall device and process requirements. As discussed above, the metallization system 150 may comprise a plurality of metallization layers, depending on the overall complexity of the device 100. For convenience, a metallization layer 160 is illustrated in FIG. 1 a, followed by a further metallization layer 170, in which appropriate interconnect structures are still to be formed. The metallization layer 160 may comprise an appropriate dielectric material 161, which may include low-k dielectric materials, ULK dielectric materials and the like, possibly in combination with conventional dielectric materials, depending on the overall complexity of the metallization system 150. It should be appreciated that, in sophisticated applications and in particular in low power applications, typically a low-k dielectric material may be implemented in the dielectric layer 161. Moreover, a plurality of metal regions 162, which may also be referred to as metal lines or interconnect structures, may be provided so as to be embedded in the dielectric material 161. Furthermore, a cap or etch stop layer 163 may be formed above the dielectric material 161 and the metal regions 162. In some illustrative embodiments, the layer 163 may be directly formed on the metal regions 162, thereby acting as a dielectric barrier material, while in other cases a dedicated conductive barrier material may be formed as a top portion (not shown) of the metal regions 162. For example, the layer 163 may be comprised of silicon dioxide, nitrogen-containing silicon carbide, silicon nitride and the like.

It should be appreciated that the metal regions 162 may comprise highly conductive core metal 162A, such as a copper material and the like, which may be confined by a conductive barrier layer 162B, which, in some illustrative embodiments, may be comprised of a copper/silicon compound in order to provide superior electromigration and electrical performance, as is already discussed above.

The metallization layer 170 in this manufacturing stage may comprise a dielectric material 171, which may also comprise a low-k dielectric material or a ULK material in sophisticated applications, which may be formed on or above the layer 163. Moreover, an opening of an interconnect structure 172 may be provided in the dielectric material 171. For example, a trench 171T in combination with a via opening 171V may be provided so as to connect to one of the metal regions 162. It should be appreciated, however, that the openings 171T, 171V may have any appropriate configuration as required by the overall layout of the metallization layer 170.

The semiconductor device 100 as illustrated in FIG. 1 a may be formed on the basis of the following process strategy. The circuit elements 121 in the device level 120 may be formed by using any appropriate process techniques, including sophisticated lithography processes, deposition processes, etch techniques, planarization processes, implantation sequences, anneal processes and the like. For example, the circuit elements 121 may be formed, according to some illustrative embodiments, on the basis of critical dimensions of 50 nm and less. For example, at least some of the circuit elements 121 may be provided in the form of field effect transistors having a critical dimension of 50 nm and less. Thereafter, a contact structure (not shown) may be provided so as to act as an interface between the device level 120 and the metallization system 150. To this end, any appropriate contact technology may be applied. Next, the one or more metallization layers of the system 150 may be formed. For example, the metallization layer 150 may be formed in accordance with process techniques, as will be described in more detail with reference to the metallization layer 170. Thus, any detailed description of the respective process steps may be omitted here. Hence, after depositing the cap or etch stop layer 163, one or more appropriate materials for the dielectric layer 171 may be formed, for instance by chemical vapor deposition (CVD) techniques, spin-on techniques and the like, depending on the type of material to be used. Moreover, if required, the dielectric constant may be adjusted by applying additional treatments, for instance by producing or increasing the degree of porosity in a dielectric base material and the like. Thereafter, complex patterning strategies may be applied, including lithography processes and etch strategies based on hard mask regimes and the like, in order to form the openings 171T, 171V. In other cases, the openings 171T, 171V may be formed separately, for instance by providing a portion of the dielectric material 171 and patterning the same, followed by a subsequent deposition of respective conductive materials, as will be explained later on in more detail. In the example shown, the openings 171T, 171V may be subjected to a common process sequence for providing an appropriate fill metal in combination with a silicon and copper-based barrier material.

FIG. 1 b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, wherein, for convenience, portions of the metallization layers 170, 160 are illustrated only. As shown, a deposition process 103 may be performed according to illustrative embodiments in order to form a copper-containing material layer 172C on inner sidewalls 171S of the openings 171T, 171V. It should be appreciated, however, that the material layer 172C may also be formed at any other exposed surface areas of the dielectric material 171. Moreover, the layer 172C may be formed on exposed surface areas 162S of the metal region 162 of the metallization layer 160. In some illustrative embodiments, the layer 172C may be provided in the form of a substantially pure copper material, which may be deposited by using sputter deposition techniques and the like. In other cases, the layer 172C may have incorporated therein an additional species, such as an alloy forming species in the form of aluminum and the like, if this is considered appropriate for the silicon/copper compound on the basis of the layer 172C. A corresponding species may be incorporated during the deposition process 103 or may be incorporated, if required, during a separate process step, for instance by applying the plasma ambient and the like.

It should be appreciated that, prior to performing the deposition process 103, additional surface treatments may be performed in order to enhance the surface of the material 171, which may have been damaged during the patterning of the openings 171T, 171V, in particular when the material 171 may comprise a ULK material. To this end, well-established repair strategies may be applied, for instance by exposing the material 171 to a silicon-containing process ambient and the like.

FIG. 1 c schematically illustrates the device 100 in a further advanced manufacturing stage in which the device 100 comprising the copper-containing material layer 172B may be exposed to a silicon-containing process ambient 104, which may be established, in some illustrative embodiments, on the basis of a plasma atmosphere including an appropriate silicon-containing gas, such as silane or any similar silicon-containing gas component. Consequently, during the exposure to the ambient 104, silicon species may be incorporated into the previously deposited layer 172C (FIG. 1 b), thereby increasingly converting the base material of this layer into a copper-silicon compound, thereby forming a copper silicide. Consequently, after completing the exposure to the ambient 104, a copper-silicon compound barrier layer 172B may be formed on any exposed surface areas and, in particular, on the surface areas 171S of the openings 171T, 171V. In some illustrative embodiments, the barrier layer 172B may thus be comprised of a compound having the chemical formula Cu_(x)Si_(y), with x=0.05 . . . 0.95 and with y=0.95 . . . 0.05. It should be appreciated, however, that additional atomic species may be incorporated in the layer 172B due to any imperfections of the process 104, the previously deposited layer 172C (FIG. 1 b) and the like. In this case, any unwanted atomic species may be present with a fraction of 5 atomic percent and less. In other illustrative embodiments, as discussed above, a further atomic species, such as aluminum and the like, may be provided with a percentage of 5 atomic percent and higher, wherein, however, copper and silicon may still represent the dominant species in the barrier layer 172B.

FIG. 1 d schematically illustrates the semiconductor device 100 according to further illustrative embodiments. As illustrated, a silicon-containing material layer 172D, such as an amorphous silicon layer, may be formed on the exposed inner surface areas 171S and also on the metal region 162, which may be accomplished by applying any appropriate deposition technique. Furthermore, the copper-containing layer 172C may be formed on the layer 172D, which may be accomplished by sputter deposition techniques and the like, as is also previously explained. It should be appreciated that, in some illustrative embodiments, the layer 172D may be formed during and after a process sequence for enhancing the overall surface conditions of the dielectric material 171, for instance, on the basis of repair chemicals including HMDS and the like. In this manner, the resulting surface may be hardened, thereby avoiding undue copper penetration during the deposition of the layer 172C.

FIG. 1 e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a treatment 105 may be applied so as to initiate the interdiffusion of silicon and copper species of the previously deposited layers in order to increasingly form the desired copper/silicon compound barrier layer 172B. For example, the process atmosphere 105 may be established on the basis of elevated temperatures in a range of 100-300° C. and higher, while in other cases a plasma ambient may be established so as to initiate desired diffusion activity. In some cases, the process 105 may be applied in the presence of a silicon-containing precursor gas, thereby providing superior efficiency in forming the copper/silicon barrier layer 172B.

FIG. 1 f schematically illustrates the semiconductor device 100 according to further illustrative embodiments. As shown, the copper-containing material layer 172C may be formed on the inner sidewall surface areas 171S by any appropriate deposition technique, as is also discussed above. Thereafter, a specific silicon-containing material layer 172E may be formed in a highly controllable manner, which, in some illustrative embodiments, may be accomplished by using an appropriate carrier material, such as triazol or benzene triazol, which may have incorporated therein a silicon species. It is well known that triazol and derivatives thereof may preferably adhere to a copper surface and may thus form a well-defined surface layer in a reliable manner. Consequently, after the deposition of the carrier layer including the silicon species, an appropriate treatment 106 may be applied so as to release the silicon species and to initiate a silicon diffusion into the underlying copper-containing material layer 172C. To this end, a decomposition of the carrier material may be initiated, for instance by elevated temperatures, such as several hundred degrees Celsius, by UV radiation and the like, so that remaining silicon species may be incorporated into the layer 172C. Since the layer 172E may be provided with a well-defined layer thickness, also a well-defined amount of silicon may be incorporated into the layer 172C. If desired, the deposition of the material layer 172E may be repeated in order to further incorporate the silicon species in a highly controllable manner. In this manner, reliable formation of a copper/silicon compound may be accomplished at any device area, for instance within the via opening 171V and in particular at the exposed surface 162S of the metal region 162.

FIG. 1 g schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the interconnect structure 172 may comprise the copper/silicon barrier material 172B, which may be formed on the basis of any of the above-described process strategies, wherein, in some illustrative embodiments, the barrier layer 172B may comprise an additional layer or layer portion, such as a silicon layer portion as is, for example, shown in FIG. 1 e, depending on the applied process strategy. In other cases, the copper/silicon compound may form an interface between the dielectric material 171 and a highly conductive core metal 172A, such as a copper material. Similarly, the conductive barrier layer 172B may also be provided as an interface between the metal region 162 and the interconnect structure 172, i.e., between a via 172V and the metal region 162. Since generally copper/silicon compound contained in a conductive barrier layer 172B may have an electrical conductivity and superior electromigration characteristics compared to conventional tantalum/tantalum nitride-based barrier materials, the electrical resistance between the metal region 162 and the interconnect structure 172 may be reduced, while nevertheless a current-induced material fusion through the interface formed by the barrier layer 172B may be reduced compared to conventional barrier systems. Similarly, any material extrusion from the metal line 172L into the dielectric material 171 may be suppressed due to the superior electromigration behavior. Consequently, for an otherwise given configuration of the metallization layers 160, 170, superior electrical performance and increased lifetime may be accomplished by providing the barrier layer 172B on the basis of a copper/silicon compound.

The semiconductor device 100 as illustrated in FIG. 1 g may be formed on the basis of any appropriate process technique which may include the electrochemical deposition of the core metal by applying electroless deposition techniques, electroplating or any combination thereof. In some illustrative embodiments, the core metal 172A may be directly deposited on the conductive barrier material 172B and thus, in some illustrative embodiments, the metal 172A may be deposited directly on a copper/silicon compound. In other illustrative embodiments, a dedicated seed layer (not shown) may be formed, for instance by sputter deposition and the like, prior to filling in the core metal 172A. Thereafter, any excess material may be removed, for instance by chemical mechanical polishing (CMP), electro CMP, etching and the like, thereby also removing any residues of the conductive barrier material 172B. Thus, the interconnect structure 172 may be provided as an electrically isolated feature of the metallization layer 170. Thereafter, the further processing may be continued by forming a cap layer, such as a dielectric cap layer or a conductive cap layer on the interconnect feature 172. For example, a dielectric material, such as the material 163, may be formed so as to confine the core metal 172A, possibly in combination with a specific conductive cap material, which may be provided on the basis of electroless deposition techniques, if required. In some illustrative embodiments, also a copper/silicon compound may be formed at the surface of the interconnect structure 172 prior to depositing a dielectric material, which may be accomplished by applying similar process techniques, as are also discussed above with respect to the barrier layer 172B.

It should be appreciated that the metallization layer 160 may be formed on the basis of principles as disclosed above with respect to the metallization layer 170. In this case, also the barrier layer 162B may be provided so as to comprise a copper/silicon compound, thereby also imparting superior electromigration and electrical performance to the metal region 162.

As a result, the present disclosure provides manufacturing techniques and semiconductor devices in which a copper/silicon compound may be used as an efficient barrier material in complex metallization systems of semiconductor devices, thereby increasing the overall time to failure of the metallization system, while at the same time superior electrical performance may be obtained compared to conventional tantalum/tantalum nitride barrier systems.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below. 

1-20. (canceled)
 21. A semiconductor device, comprising: a first metallization layer positioned above a substrate of said semiconductor device, said metallization layer comprising a dielectric material and a copper-containing metal region embedded in said dielectric material; and a conductive barrier layer positioned along substantially an entirety of an interface between said copper-containing metal region and said dielectric material, said conductive barrier layer comprising a copper/silicon compound that is in direct contact with said dielectric material along substantially said entirety of said interface.
 22. The semiconductor device of claim 21, further comprising a via connecting said copper-containing metal region with a second metal region formed in a second metallization layer that is positioned below said first metallization layer, wherein said conductive barrier layer extends to a bottom of said via so as to separate said via from said second metal region.
 23. The semiconductor device of claim 22, wherein said via is embedded in said dielectric material of said first metallization layer, said copper/silicon compound comprising said conductive barrier layer being in direct contact with said dielectric material along substantially said entirety of a sidewall interface between said via and said dielectric layer.
 24. The semiconductor device of claim 21, wherein said conductive barrier layer comprises a silicon layer disposed along at least a portion of said interface.
 25. The semiconductor device of claim 21, wherein an atomic percent concentration of any non-silicon species and any non-copper species comprising said conductive barrier layer is less than 5 atomic percent relative to a combined atomic percent concentration of silicon and copper comprising said conductive barrier layer.
 26. The semiconductor device of claim 21, further comprising a cap layer positioned above said dielectric material and said copper-containing metal region.
 27. The semiconductor device of claim 21, wherein said copper/silicon compound comprises copper silicide.
 28. The semiconductor device of claim 21, wherein said dielectric material comprises a low-k dielectric material having a relative permittivity of 3.0 or less.
 29. A semiconductor device, comprising: a layer of dielectric material positioned above a semiconductor substrate; and interconnect structure embedded in said layer of dielectric material, said interconnect structure comprising: a metal region; and a copper silicide barrier layer positioned between said layer of dielectric material and said metal region, said copper silicide barrier layer extending along substantially an entirety of an interface between said metal region and said layer of dielectric material, wherein said copper silicide barrier layer is in direct contact with said layer of dielectric material along substantially said entirety of said interface.
 30. The semiconductor device of claim 29, wherein said metal region comprises copper.
 31. The semiconductor device of claim 29, wherein said interconnect structure comprises at least one of a conductive line and a conductive via.
 32. The semiconductor device of claim 29, further comprising a dielectric cap layer positioned above an upper surface of said layer of dielectric material and above an upper surface of said interconnect structure.
 33. The semiconductor device of claim 29, wherein said interconnect structure and said layer of dielectric material comprise a first metallization layer of a metallization system of said semiconductor device, said semiconductor device further comprising a second metallization layer of said metallization system positioned below said first metallization layer.
 34. The semiconductor device of claim 33, wherein said second metallization layer comprises a second layer of dielectric material and a second metal region embedded in said second layer of dielectric material, said interconnect structure directly contacting said second metal region.
 35. The semiconductor device of claim 34, wherein said copper silicide barrier layer extends along an interface between said interconnect structure and said second metal region.
 36. The semiconductor device of claim 34, further comprising a dielectric cap layer positioned between said first and second metallization layers.
 37. The semiconductor device of claim 34, wherein at least one of said layer of dielectric material and said second layer of dielectric material comprises a low-k dielectric material having a relative permittivity of 3.0 or less.
 38. The semiconductor device of claim 34, wherein said second metal region comprises copper. 